Hardware/Software Codesign on Platform
describes design techniques for mapping complex, system-on-chip-like
designs on Field Programmable Gate Arrays. Such designs typically
contain one or more embedded processors, as well as a range of
custom-designed hardware modules. The challenge, for the designer, to design such systems is how to combine the design of software with hardware, and/or how to partition a given software functionality into software and hardware modules such that the overall system throughput is optimized. In addition, constraints such as area, interfaces, communication bandwidth, memory-space, often need to be taken into account as well.
The two-and-a-half day course (Wednesday afternoon until Friday evening) on Hardware/Software Codesign introduces the key ideas in hardware/software codesign, including system-modeling, analysis of system-level description, system-level architecture customization and optimization. The course covers hardware/software integration techniques, and comes with hands-on sessions on an FPGA design kit. Participants will familiarize themselves with a modern FPGA design flow based on Altera chips.
Participants will receive course lecture materials,
the design examples from the hands-on sessions,
and the FPGA design kit.
The two-and-a-half day course handles three major topics.
Day 1: Once-Over-Lightly
- Hardware/Software Codesign: Why do we care?
- The Role of Modeling and Abstraction
- FPGA Technologies, Hardware and Software
- Design Flow for Hardware/Software Codesign
- Handson: Altera SOPC Builder, Platform Simulation
Day 2: Modeling and Architecture Design
- Dataflow Modeling for System Design
- Performance-enhancing Transformations in Dataflow
- Mapping Dataflow into Hardware and Software Implementation
- Control/Dataflow Analysis of C Programs
- Custom Platform Architectures
- On-chip Bus Systems
- Handson: Performance Analysis and Debugging of SoC Designs
Day 3: Interfaces and Coprocessor Design
- Custom-Instruction Interfaces
- Memory-Mapped Interfaces
- Coprocessor Design Flow: Analysis, Transformations, Refinement
- Design Verification using Cosimulation
- Design Examples
- Handson: Performance Optimization of a Cryptographic Application
- Designers who are already using FPGA in their current design flow, and who wish to evaluate the impact of hardware/software codesign techniques on modern FPGA design.
- Embedded-system implementers who are evaluating the potential of FPGA next to standard embedded components.
- Technical group leaders involved in design flow definition using modern embedded components.
- Students, researchers and practitioners in hardware/software codesign for FPGA.
- Dates: June 27 (Wednesday) to June 29 (Friday), 2012
Location: Virgnia Tech Research Center,
Nearby hotels include the Westin Arlington Gateway and the Holiday Inn – Ballston
- Registration: The cost of the course is $1800. This includes two-and-a-half days of lecture, lecture materials, and coffee breaks. Discounts are available for multiple registrations. Participants can register through the Virginia Tech Continuing and Professional Education website.
- Questions on CESCA's Continuing Education program can be directed to Patrick Schaumont (firstname.lastname@example.org)