ECE: Electrical & Computer Engineering
Hardware/Software Codesign

Hardware/Software Codesign on Platform FPGA's


Content Audience Instructor Venue
CESCA Logo
Short Course Series
Registration

Date:
6/27-6/29, 2012 Location:
Arlington, VA Contact:
Patrick Schaumont
schaum@vt.edu

Course Information

Hardware/Software Codesign on Platform FPGA's
describes design techniques for mapping complex, system-on-chip-like
designs on Field Programmable Gate Arrays. Such designs typically
contain one or more embedded processors, as well as a range of
custom-designed hardware modules. The challenge, for the designer, to design such systems is how to combine the design of software with hardware, and/or how to partition a given software functionality into software and hardware modules such that the overall system throughput is optimized. In addition, constraints such as area, interfaces, communication bandwidth, memory-space, often need to be taken into account as well.

The two-and-a-half day course (Wednesday afternoon until Friday evening) on Hardware/Software Codesign introduces the key ideas in hardware/software codesign, including system-modeling, analysis of system-level description, system-level architecture customization and optimization. The course covers hardware/software integration techniques, and comes with hands-on sessions on an FPGA design kit. Participants will familiarize themselves with a modern FPGA design flow based on Altera chips.

Participants will receive course lecture materials, the design examples from the hands-on sessions, and the FPGA design kit.

Course Content

The two-and-a-half day course handles three major topics.

Day 1: Once-Over-Lightly

  • Hardware/Software Codesign: Why do we care?
  • The Role of Modeling and Abstraction
  • FPGA Technologies, Hardware and Software
  • Design Flow for Hardware/Software Codesign
  • Handson: Altera SOPC Builder, Platform Simulation

Day 2: Modeling and Architecture Design

  • Dataflow Modeling for System Design
  • Performance-enhancing Transformations in Dataflow
  • Mapping Dataflow into Hardware and Software Implementation
  • Control/Dataflow Analysis of C Programs
  • Custom Platform Architectures
  • On-chip Bus Systems
  • Handson: Performance Analysis and Debugging of SoC Designs

Day 3: Interfaces and Coprocessor Design

  • Custom-Instruction Interfaces
  • Memory-Mapped Interfaces
  • Coprocessor Design Flow: Analysis, Transformations, Refinement
  • Design Verification using Cosimulation
  • Design Examples
  • Handson: Performance Optimization of a Cryptographic Application

Target Audience

The course is targeted at a broad audience in Electronic Engineering. Potential participants may include:
  • Designers who are already using FPGA in their current design flow, and who wish to evaluate the impact of hardware/software codesign techniques on modern FPGA design.
  • Embedded-system implementers who are evaluating the potential of FPGA next to standard embedded components.
  • Technical group leaders involved in design flow definition using modern embedded components.
  • Students, researchers and practitioners in hardware/software codesign for FPGA.

About the Instructor

Patrick Schaumont is Associate Professor in Computer Engineering at Virginia Tech. He received the PhD degree in Electrical Engineering from UCLA (2004). At Virginia Tech, he is leading the Secure Embedded Systems group. His research, supported by NSF and NIST, covers design and methodologies for secure embedded systems. He is author of the book "A Practical Introduction to Hardware/Software Codesign," used for several senior-level and graduate-level University courses including at Virginia Tech. He has served on the program committee of international conferences in the field of embedded system design, including CHES, DATE, DAC, IEEE HOST and IEEE MEMOCODE, and as guest editor for IEEE Design and Test Magazine, ACM Transactions on Reconfigurable Technology and Systems, and IEEE Transactions on Computer-Aided Design of Integrated Circuits. He has published over 100 papers, a book, and 4 patents. He is a senior member of the IEEE.

Patrick Schaumont

Course Dates and Location

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