Power Analysis on FPGA

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GEZEL
Hardware/Software Codesign Environment

GEZEL is a cycle-based hardware description language based on the Finite-State-Machine + Datapath (FSMD) model. The GEZEL tools offer stand-alone simulation, cosimulation, and code-generation into synthesizable (VHDL) code. Through user-defined library-block extensions in C++, new cosimulation interfaces can be added. GEZEL is open-source.

Highlights:

  • Cycle-based hardware simulation engine.
  • Scripted environment with easy-to-learn hardware description language.
  • Cosimulation with embedded cores, such as ARM, 8051, AVR.
  • Code generator for synthesizable VHDL code.
  • Free.

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