From Gezel2

RAM modules are modeled in GEZEL using ipblock constructs. The RAM ipblock emulates the default behavior of Xilinx BlockRAM Module. For a list of available ipblocks, refer to GEZEL Library Blocks.

ramblock.fdl

// RAM cell
ipblock M(in address : ns(5);
          in wr,rd   : ns(1);  
          in idata   : ns(36);
          out odata  : ns(36)) {
  iptype "ram";
  ipparm "wl=8";  
  ipparm "size=36";  
}
 
dp tmac(out address : ns(5);
   out wr, rd  : ns(1);
   out idata   : ns(36);
   in odata    : ns(36)) {
   reg ar : ns(5);
   reg idr, odr : ns(36);
   sfg write  { wr = 1; rd = 0; idata = idr; odr = odata; address = ar;  
                $display($cycle, ":ar ", ar, " idata ", idata); }
   sfg read   { wr = 0; rd = 1; address = ar; odr = odata; idata = idr;  
                $display($cycle, ":ar ", ar, " odata ", odata); }
   sfg incadr { ar = ar + 1; idr = idr + 1;}
   sfg clraddr { ar = 0; }
}
 
fsm ftmac(tmac) {
  state   s1;
  initial s0;
  @s0 if (ar == 8) then (write, clraddr ) -> s1;
  else   (write, incadr)  -> s0;
  @s1 if (ar == 8) then (read,  clraddr)  -> s0;
  else   (read,  incadr)   -> s1;
}
 
dp ramblock_sys {
  sig adr  : ns(5);
  sig w, r : ns(1);
  sig i, o : ns(36);
  use M   (adr, w, r, i, o);
  use tmac(adr, w, r, i, o);
} 

system S {
  ramblock_sys;
}

Simulation Output

>fdlsim ramblock.fdl 30
ram: set wl 8
ram: set size 36
0:ar 0/1 idata 0
1:ar 1/2 idata 1
2:ar 2/3 idata 2
3:ar 3/4 idata 3
4:ar 4/5 idata 4
5:ar 5/6 idata 5
6:ar 6/7 idata 6
7:ar 7/8 idata 7
8:ar 8/0 idata 8
9:ar 0/1 odata 0
10:ar 1/2 odata 0
11:ar 2/3 odata 1
12:ar 3/4 odata 2
13:ar 4/5 odata 3
14:ar 5/6 odata 4
15:ar 6/7 odata 5
16:ar 7/8 odata 6
17:ar 8/0 odata 7
18:ar 0/1 idata 10
19:ar 1/2 idata 11
20:ar 2/3 idata 12
21:ar 3/4 idata 13
22:ar 4/5 idata 14
23:ar 5/6 idata 15
24:ar 6/7 idata 16
25:ar 7/8 idata 17
26:ar 8/0 idata 18
27:ar 0/1 odata 8
28:ar 1/2 odata 10
29:ar 2/3 odata 11