SHA-FPGA
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SHA-FPGA is a standardized testbench tool for hardware implementations of hashing algorithms.
[edit] Interface Definition
Refer to this document for the explanation of the interface.
[edit] Result Listing
| Algorithm | Flow | WL | Cycles Per Byte | Area | Clock | Throughput | Link |
|---|---|---|---|---|---|---|---|
| cubehash-8-1 | verilog | 8 | 9 (9.8) | 1156 Slices, 1049 FF | 93 MHz | package link | |
| essence 256 | gezel | 32 | 2.9 (4.25) | 1788 Slices, 1167 FF | 125 MHz | package link | |
| sha256 | gezel | 32 | 1.03 (1.30) | 1258 Slices, 1170 FF | 60 MHz | package link | |
| sha256 | verilog | 32 | 1.03 (1.30) | 1101 Slices, 1073 FF | 55 MHz | package link |
Cycles per byte - cycle count to hash 1 byte of message using the provided testbench. The first value is the time based on the cycle count for a single block of data. The second value (in parenthesise) is the value to hash 2048 bits of plaintext and includes initialization cycles needed by the hash module.
Area - Slice count and number of flip-flops obtained using ISE 8.1.
[edit] Platforms
| Software | Platform | Blank Package | Notes |
|---|---|---|---|
| ModelSim PE Student Edition | Verilog testbench | package link | |
