Performance Evaluation of Cryptographic Hardware and Software

-- Performance Evaluation of SHA-3 Candidates in ASIC and FPGA

Xu Guo, Meeta Srivastav, Sinan Huang, Dinesh Ganta, Michael B. Henry, Leyla Nazhandali, and Patrick Schaumont

Center for Embedded Systems for Critical Applications (CESCA), ECE, Virginia Tech

Project Sponsor: National Institute of Standards and Technology (NIST)

none
Home
Publications
SHA-3 Chip
Source Codes
Related Work
   
People

Professors: Patrick Schaumont, Leyla Nazhandali

Current Members : Xu "Eric" Guo (PhD), Meeta Srivastav(PhD), Yongbo Zuo(MS), Dinesh Ganta(PhD)

Alumni: Sinan Huang(MS), Michael B. Henry(PhD), Francisco Borelli(BS)

Affiliation: Center for Embedded Systems for Critical Applications (CESCA), ECE, Virginia Tech

Introduction

The work of performance evaluation of SHA-3 candidates in ASIC and FPGA is part of the NIST sponsored project, "Environment for Fair and Comprehensive Performance Evaluation of Cryptographic Hardware and Software" (link) . This webpage list all the publications, source codes and scripts related to the SHA-3 hardware benchmarking work completed at Virgnia Tech. [VT-SHA3 Website Citation BibTex]

News
02/28/2012: Our invited paper, titled "Design and Benchmarking of an ASIC with Five SHA-3 Finalist Candidates", got accepted in a special issue of Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) on "Digital System Security and Safety"!
 
11/28/2011: We reported the first SHA-3 ASIC measurement results based on SASEBO-R board in our newly accepted DATE2012 conference paper!
 
11/11/2011: We have approved 8 chip requests in the last two months and more are pending. Currently, our SHA-3 ASIC are under various performance and security evalulation in research groups from USA, UK, Belgium, Germany, Hong Kong, and Japan. If you are interested in evaluating our SHA-3 ASIC, please file your application here soon.
 

08/17/2011: The VT SHA-3 chip has been fabricated, packaged and fully tested. It contains a total of five SHA-3 finalists with Round 3 specifications (updated in Jan., 2011) and a reference SHA256 as below:

 
  • BLAKE-256
  • Groestl-256
  • JH-256
  • Keccak-256
  • Skein512-256
  • SHA256

  • Free SHA-3 sample chips are available upon request.
  • Check here for more information.
   
 

06/27/2011: The VT SHA-3 chip was back from MOSIS and packaged with 160-pin 28x28 QFP Open Cavity Package. The chip is now under fully testing on the SASEBO-R board.

 

02/15/2011: Our SHA-3 ASIC chip has been sent out for tape-out by IBM MOSIS 130nm CMR8SF-RVT Process with ARM's Artisan SAGE-X v2.0 standard-cell library. It is highly possible that it will be the first SHA-3 ASIC chip implementing all the SHA-3 five finalists with the latest Round 3 specifications.

 

12/09/2010: NIST has selected five SHA-3 candidates to advance to the third (and final) round:

  • BLAKE
  • Groestl
  • JH
  • Keccak
  • Skein

Link: NIST Status Report on the Second Round of the SHA-3 Cryptographic Hash Algorithm Competition

 
11/19/2010: Release VT-SHA3 website with all the opensourced RTL codes, simulation files, and FPGA/ASIC scripts of SHA-3 Second Round 14 candidates (link).
 
Home
Publications
SHA-3 Chip
Source Codes
Related Work

Last updated on: December 2, 2011

Comments about this website to: Xu "Eric" Guo <xuguo@vt.edu >

www.free-counter-plus.com

since Nov. 19. 2010