Performance Evaluation of Cryptographic Hardware and Software
-- Performance Evaluation of SHA-3 Candidates in ASIC and FPGA
Xu Guo, Meeta Srivastav, Sinan Huang, Dinesh Ganta, Michael B. Henry, Leyla Nazhandali, and Patrick Schaumont
Center for Embedded Systems for Critical Applications (CESCA), ECE, Virginia Tech
Project Sponsor: National Institute of Standards and Technology (NIST)
Publications
Copyright Notice: These materials are presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights are retained by authors or by other copyright holders.
M. Srivistav, X. Guo, S. Huang, D. Ganta, M. B. Henry, L. Nazhandali, and P. Schaumont, "Design and Benchmarking of an ASIC with Five SHA-3 Finalist Candidates," Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), 2012. (Invited Paper in a Special Issue on "Digital System Security and Safety")
X. Guo, M. Srivistav, S. Huang, D. Ganta, M. B. Henry, L. Nazhandali, and P. Schaumont, "ASIC Implementations of Five SHA-3 Finalists," Design, Automation and Test in Europe (DATE2012), March 2012. [BibTeX]
X. Guo and P. Schaumont, "The Technology Dependence of Lightweight Hash Implementation Cost," ECRYPT Workshop on Lightweight Cryptography (LC2011), November 2011. [BibTeX]
X. Guo, M. Srivistav, S. Huang, D. Ganta, M. B. Henry, L. Nazhandali, and P. Schaumont, "Pre-silicon Charaterization of NIST SHA-3 Final Round Candidates," 14th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2011), August 2011. [BibTeX]
X. Guo, M. Srivistav, S. Huang, D. Ganta, M. B. Henry, L. Nazhandali, and P. Schaumont, "Silicon Implementation of SHA-3 Finalists: BLAKE, Grostl, JH, Keccak and Skein," ECRYPT II Hash Workshop 2011, May 2011. [BibTeX]
Z. Chen, X. Guo, A. Sinha, and P. Schaumont, "Data-Oriented Performance Analysis of SHA-3 Candidates on FPGA Accelerated Computers," Design, Automation and Test in Europe (DATE2011), 2011. [BibTex]
X. Guo, S. Huang, L. Nazhandali, P. Schaumont, "On The Impact of Target Technology in SHA-3 Hardware Benchmark Rankings," Cryptology ePrint Archive, Report 2010/536, 2010. [BibTex]
X. Guo, S. Huang, L. Nazhandali, P. Schaumont, "Fair and Comprehensive Performance Evaluation of 14 Second Round SHA-3 ASIC Implementations," NIST 2nd SHA-3 Candidate Conference, Aug. 2010. [BibTex]
K. Kobayashi, J. Ikegami, M. Knezevid, X. Guo, S. Matsuo, S. Huang, L. Nazhandali, U. Kocabas, J. Fan, A. Satoh, I. Verbauwhede, K. Sakiyama, K. Ota, "A Prototyping Platform for Performance Evaluation of SHA-3 Candidates," IEEE International Symposium on Hardware-Oriented Security and Trust (HOST2010) , Jun. 2010. [BibTex]
Z. Chen, S. Morozov, P. Schaumont, "A Hardware Interface for Hashing Algorithms," ePrint IACR Archive, 2008/529, December 2008. [BibTex]
Posters
X. Guo, M. Srivistav, S. Huang, D. Ganta, Michael Henry, L. Nazhandali, and P. Schaumont, "Benchmarking ASIC with Five NIST SHA-3 Finalists," Workshop on Cryptographic Hardware and Embedded Systems (CHES 2011) Exhibition Poster, September 2011. [BibTex]
X. Guo, Meeta Srivistav, S. Huang, L. Nazhandali, and P. Schaumont, "VLSI Characterization of NIST SHA-3 Finalists", 48th Design Automation Conference (DAC 2011) Work-In-Progress (WIP), June 2011. [BibTeX]
S. Huang, X. Guo, Meeta Srivistav, Dinesh Ganta, L. Nazhandali, and P. Schaumont, "Hardware Evaluation of SHA-3 Candidates", Annual Workshop of Virginia Tech's Center for Embedded Systems for Critical Applications (CESCA), May 2011.
X. Guo, S. Huang, Meeta Srivistav, L. Nazhandali, and P. Schaumont, "The Role of Storage Structures in Lightweight Cryptography", Annual Workshop of Virginia Tech's Center for Embedded Systems for Critical Applications (CESCA), May 2011.
K. Kobayashi, J. Ikegami, M. Knezevid, X. Guo, S. Matsuo, S. Huang, L. Nazhandali, U. Kocabas, J. Fan, A. Satoh, I. Verbauwhede, K. Sakiyama, K. Ota, "A Prototyping Platform for Performance Evaluation of SHA-3 Candidates", IEEE International Symposium on Hardware-Oriented Security and Trust (HOST2010) , Jun. 2010.
X. Guo, S. Huang, L. Nazhandali, and P. Schaumont, "Crypto Hardware Benchmark: from SHA-FPGA to SHA-ASIC", Annual Workshop of Virginia Tech's Center for Embedded Systems for Critical Applications (CESCA), May 2010.
Presentations
Xu Guo, "Fair and Comprehensive Performance Evaluation of SHA-3 Hardware Implementations", CESCA Seminar, ECE Department, Virginia Tech, September 2010.
Patrick Schaumont , "Fair and Comprehensive Performance Evaluation of 14 Second Round SHA-3 ASIC Implementations", NIST 2nd SHA-3 Candidate Conference, Aug. 2010.
Last updated on: Feb. 28, 2011 Comments about this website to: Xu "Eric" Guo <xuguo@vt.edu >
since Nov. 19. 2010 |
