Performance Evaluation of Cryptographic Hardware and Software

-- Performance Evaluation of SHA-3 Candidates in ASIC and FPGA

Xu Guo, Meeta Srivastav, Sinan Huang, Dinesh Ganta, Michael B. Henry, Leyla Nazhandali, and Patrick Schaumont

Center for Embedded Systems for Critical Applications (CESCA), ECE, Virginia Tech

Project Sponsor: National Institute of Standards and Technology (NIST)

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SHA-3 Hardware Publications

This is a comprehensive collection of the SHA-3 hardware related publications for Round 2 and Round 3 (Final Round) candidates. (Last updated on Feb. 5, 2012)

Note: If you think there are important references missing in the list below, please kindly send us emails (sha3vt@gmail.com) and we will update soon. Thanks.

  NIST SHA-3 Third (Final) Round Candidates with Round 3 Tweaks
  2012
[PDF]
X. Guo, M. Srivistav, S. Huang, D. Ganta, M. B. Henry, L. Nazhandali, and P. Schaumont, "ASIC Implementations of Five SHA-3 Finalists," Design, Automation and Test in Europe (DATE2012), March 2012. (ASIC)
  2011
[PDF]
G. Provelengios, N. Voros and P. Kitsos, "Low Power FPGA Implementations of JH and Fugue Hash Functions," 14th Euromicro Conference on Digital Systems (DSD'11), Oulu, Finland, August 31 - September 2, 2011. (FPGA)
[PDF]
Ekawat Homsirikamol, Marcin Rogawski, and Kris Gaj, "Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs," CHES2011, LNCS6917, pp.491-506, 2011. (FPGA)
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Nicolas Sklavos, "Multi-module Hashing System for SHA-3 & FPGA Integration," 21st International Conference on Field Programmable Logic and Applications (FPL'11), September 2011. (FPGA)
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X. Guo, M. Srivistav, S. Huang, D. Ganta, M. B. Henry, L. Nazhandali, and P. Schaumont, "Pre-silicon Characterization of NIST SHA-3 Final Round Candidates," 14th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2011), August, 2011. (ASIC)
[PDF]
X. Guo, M. Srivistav, S. Huang, L. Nazhandali, and P. Schaumont, "VLSI Characterization of NIST SHA-3 Finalists," 48th Design Automation Conference (DAC 2011) Work-In-Progress (WIP), June 2011. (ASIC)
[PDF]
E. Homsirikamol, M. Rogawski, and K. Gaj, "Comparing Hardware Performance of Round 3 SHA-3 Candidates Using Multiple Hardware Architecture in Xilinx and Altera FPGAs," in CRYPT II Hash Workshop 2011, May 2011. (FPGA)
[PDF]
M. U. Sharif, R. Shahid, M. Rogawski, and K. Gaj, "Use of Embedded FPGA Resources in Implementations of Five Round Three SHA-3 Candidates," in CRYPT II Hash Workshop 2011, May 2011. (FPGA)
[PDF]
B. Jungk, "Compact Implementations of Grostl, JH and Skein for FPGAs," in CRYPT II Hash Workshop 2011, May 2011. (FPGA)
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S. Kerckhof, F. Durvaux, N. Veyrat-Charvillon, F. Regazzoni, G. M. D. Dormaele, and F.-X. Standaert, "Compact FPGA Implementations of the Five SHA-3 Finalists," in CRYPT II Hash Workshop 2011, May 2011. (FPGA)
[PDF]
X. Guo, M. Srivistav, S. Huang, D. Ganta, M. B. Henry, L. Nazhandali, and P. Schaumont, "Silicon Implementation of SHA-3 Finalists: BLAKE, Grostl, JH, Keccak and Skein," in ECRYPT II Hash Workshop 2011, May 2011. (ASIC)
  NIST SHA-3 Second Round Candidates with Round 2 Tweaks
  2011
[PDF]
X. Guo and P. Schaumont, "The Technology Dependence of Lightweight Hash Implementation Cost," ECRYPT Workshop on Lightweight Cryptography (LC2011), November 2011. (ASIC)
[PDF]
Z. Chen, X. Guo, A. Sinha, and P. Schaumont, "Data-Oriented Performance Analysis of SHA-3 Candidates on FPGA Accelerated Computers", Design, Automation and Test in Europe (DATE2011), 2011. (FPGA)
[PDF]
Jean-Luc Beuchat, Eiji Okamoto and Teppei Yamazaki, "A low-area unified hardware architecture for the AES and the cryptographic hash function ECHO," Journal of Cryptographic Engineering, pp.1-21, 2011. (FPGA)
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M. Knezevic, K. Kobayashi, J. Ikegami, S. Matsuo, A. Satoh, U. Kocabas, J. Fan, T. Katashita, T. Sugawara, K. Sakiyama, I. Verbauwhede, K. Ohta, N. Homma and T. Aoki, "Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on PP(99): 1-13, 2011. (ASIC & FPGA)
[PDF]
Jeremie Detrey, Pierrick Gaudry and Karim Khalfallah, "A low-area yet performant FPGA implementation of Shabal," Selected Areas in Cryptography (SAC2010), LNCS 6544, pp.99-113, 2011. (FPGA)
  2010
[PDF]
P. Kitsos, N. Sklavos, A. N. Skodras, "Low Power FPGA Implementations of 256-bit Luffa Hash Function," 13th Euromicro Conference on Digital Systems (DSD 2010), Lille, France, September 1-3, 2010. (FPGA)
[PDF]
X. Guo, S. Huang, L. Nazhandali, and P. Schaumont, "On The Impact of Target Technology in SHA-3 Hardware Benchmark Rankings," Cryptology ePrint Archive, Report 2010/536, 2010. (ASIC & FPGA)
[PDF]
K. Kobayashi, J. Ikegami, M. Knezevid, X. Guo, S. Matsuo, S. Huang, L. Nazhandali, U. Kocabas, J. Fan, A. Satoh, I. Verbauwhede, K. Sakiyama, and K. Ota, "Prototyping Platform for Performance Evaluation of SHA-3 Candidates," IEEE International Symposium on Hardware-Oriented Security and Trust (HOST2010) , Jun. 2010. (FPGA)
[PDF]
X. Guo, S. Huang, L. Nazhandali and P. Schaumont, "Fair and Comprehensive Performance Evaluation of 14 Second Round SHA-3 ASIC Implementations," NIST 2nd SHA-3 Candidate Conference, Aug. 2010. (ASIC)
[PDF]
Brian Baldwin, Neil Hanley, Mark Hamilton, Liang Lu, Andrew Byrne, Maire O'Neill and William P. Marnane," FPGA Implementations of the Round Two SHA-3 Candidates," NIST 2nd SHA-3 Candidate Conference, Aug. 2010. (FPGA)
[PDF]
Mohamed El-Hadedy, Martin Margala, Danilo Gligoroski and Svein J. Knapskog, "Resource-Efficient Implementation of ˇ°Blue Midnight Wish-256ˇ± Hash Function on Xilinx FPGA Platform," NIST 2nd SHA-3 Candidate Conference, Aug. 2010. (FPGA)
[PDF]
Julien Francq and Celine Thuillet, "Unfolding Method for Shabal on Virtex-5 FPGAs: Concrete Results," NIST 2nd SHA-3 Candidate Conference, Aug. 2010. (FPGA)
[PDF]
Kris Gaj, Ekawat Homsirikamol, and Marcin Rogawski, "Comprehensive Comparison of Hardware Performance of Fourteen Round 2 SHA-3 Candidates with 512-bit Outputs Using Field Programmable Gate Arrays," NIST 2nd SHA-3 Candidate Conference, Aug. 2010. (FPGA)
[PDF]
Kris Gaj, Jens-Peter Kaps, Venkata Amirineni, Marcin Rogawski, Ekawat Homsirikamol, "ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Algorithms using FPGAs," NIST 2nd SHA-3 Candidate Conference, Aug. 2010. (FPGA)
[PDF]
Kimmo U. Jarvinen, "Sharing Resources Between AES and the SHA-3 Second Round Candidates Fugue and Grostl," NIST 2nd SHA-3 Candidate Conference, Aug. 2010. (FPGA)
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Shin'ichiro Matsuo, Miroslav Knezevic, Patrick Schaumont, Ingrid Verbauwhede, Akashi Satoh, Kazuo Sakiyama and Kazuo Ota, "How Can We Conduct Fair and Consistent Hardware Evaluation for SHA-3 Candidate?," NIST 2nd SHA-3 Candidate Conference, Aug. 2010. (FPGA)
[PDF]
Abdulkadir Akin, Aydin Aysu, Onur Can Ulusel, and Erkay Savas, "Efficient Hardware Implementation of high Throughput SHA-3 Candidates Keccak, Luffa and Blue Midnight Wish for Single- and Multi-Message Hashing," NIST 2nd SHA-3 Candidate Conference, Aug. 2010. (ASIC & FPGA)
[PDF]
Stefan Tillich, Martin Feldhofer, Mario Kirschbaum, Thomas Plos, Joern-Marc Schmidt, and Alexander Szekely, "Uniform Evaluation of Hardware Implementations of the Round-Two SHA-3 Candidates," NIST 2nd SHA-3 Candidate Conference, Aug. 2010. (ASIC)
[PDF]
Jesse Walker, Farhana Sheikh, Sanu K. Mathew, Ram Krishnamurthy, "A Skein-512 Hardware Implementation," NIST 2nd SHA-3 Candidate Conference, Aug. 2010. (ASIC)
[PDF]
Nicolas Sklavos and Paris Kitsos, "BLAKE HASH Function Family on FPGA: From the Fastest to the Smallest," 2010 IEEE Annual Symposium on VLSI, pp.139-142, July 2010. (FPGA)
[PDF]
A. H. Namin, G. Li, J. Wu, J. Xu, Y. Huang, O. Nam, R. Elbaz and M. A. Hasan, "FPGA Implementation of CubeHash, Grostel, JH,and SHAvite-3 Hash Functions," 2010 8th IEEE International NEWCAS Conference (NEWCAS), pp.121-124, June 2010. (FPGA)
[PDF]
Namin, A.H. and Hasan, M.A., "Implementation of the compression function for selected SHA-3 candidates on FPGA," 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), April, 2010. (FPGA)
[PDF]
Paris Kitsos and Nicolas Sklavos, "On the Hardware Implementation Efficiency of SHA-3 Candidates," 2010 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Dec. 2010. (FPGA)
[PDF]
Kazuyuki Kobayashi, Jun Ikegami, Shin'ichiro Matsuo, Kazuo Sakiyama and Kazuo Ohta, "Evaluation of Hardware Performance for the SHA-3 Candidates Using SASEBO-GII," Cryptology ePrint Archive, Report 2010/010, 2010. (FPGA)
[PDF]
Elif Bilge Kavun and Tolga Yalcin, "A Lightweight Implementation of Keccak Hash Function for Radio-Frequency Identification Applications," RFIDSec2010, LNCS6370,pp.258-269,2010. (ASIC)
[PDF]
Bernhard Jungk and Steffen Reith, "On FPGA-based implementations of the SHA-3 candidate Grostl," 2010 International Conference on Reconfigurable Computing, Dec. 2010. (FPGA)
[PDF]
Jianzhou, L. and R. Karri, "Compact hardware architectures for BLAKE and LAKE hash functions," Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May 2010. (ASIC & FPGA)
[PDF]
Luca Henzen, Pietro Gendotti, Patrice Guillet, Enrico Pargaetzi, Martin Zoller and Frank K. Gurkaynak, "Developing a Hardware Evaluation Method for SHA-3 Candidates," CHES2010, LNCS6225, pp.248-263, 2010. (ASIC)
[PDF]
Luca Henzen, Jean-Philippe Aumasson, Willi Meier, and Raphael C.-W. Phan,"VLSI Characterization of the Cryptographic Hash Function BLAKE," IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, PP(99): 1-9, 2010. (ASIC)
[PDF]
Ekawat Homsirikamol, Marcin Rogawski and Kris Gaj, "Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs," Cryptology ePrint Archive, Report 2010/445, 2010. (FPGA)
[PDF]
K. Gaj, E. Homsirikamol, and M. Rogawski, "Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs," Cryptographic Hardware and Embedded Systems - CHES 2010, LNCS 6225, pp. 264-278, Aug. 2010. (FPGA)
[PDF]
Jean-Luc Beuchat, Eiji Okamoto, and Teppei Yamazaki, "Compact Implementations of BLAKE-32 and BLAKE-64 on FPGA," 2010 International Conference on Field-Programmable Technology (FPT), 2010. (FPGA)
[PDF]
Brian Baldwin, Andrew Byrne, Liang Lu, Mark Hamilton, Neil Hanley, Maire O'Neill and William P. Marnane, "A Hardware Wrapper for the SHA-3 Hash Algorithms", IET Irish Signals and Systems Conference (ISSC 2010), June 2010. (FPGA)
[PDF]
Brian Baldwin, Andrew Byrne, Liang Lu, Mark Hamilton, Neil Hanley, Maire OˇŻNeill and William P. Marnane, "FPGA Implementations of the Round Two SHA-3 Candidates", 2010 International Conference on Field Programmable Logic and Applications, 2010. (FPGA)
[PDF]
K. Gaj, J.P. Kaps, V. Amirineni, M. Rogawski, E. Homsirikamol, B.Y. Brewster, ˇ°ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware using FPGAs,ˇ± 2010 International Conference on Field Programmable Logic and Applications, 2010. (FPGA)
[PDF]
Abdulkadir Akin, Aydin Aysu, Onur Can Ulusel and Erkay Savas, "Efficient hardware implementations of high throughput SHA-3 candidates keccak, luffa and blue midnight wish for single- and multi-message hashing," Proceedings of the 3rd international conference on Security of information and networks (SIN'10), 2010. (FPGA)
  2009
[PDF]
Stefan Tillich, "Hardware Implementation of the SHA-3 Candidate Skein," Cryptology ePrint Archive, Report 2009/159, 2009. (ASIC)
[PDF]
Stefan Tillich, Martin Feldhofer, Wolfgang Issovits, Thomas Kern, Hermann Kureck, Michael Muhlberghuber, Georg Neubauer, Andreas Reiter, Armin Kofler, and Mathias Mayrhofer, "Compact Hardware Implementations of the SHA-3 Candidates ARIRANG, BLAKE, Grostl, and Skein," Cryptology ePrint Archive, Report 2009/349, 2009. (ASIC)
[PDF]
Stefan Tillich, Martin Feldhofer, Mario Kirschbaum, Thomas Plos, Jorn-Marc Schmidt, and Alexander Szekely, "High-Speed Hardware Implementations of BLAKE, Blue Midnight Wish, CubeHash, ECHO, Fugue, Grostl, Hamsi, JH, Keccak, Luffa, Shabal, SHAvite-3, SIMD, and Skein," Cryptology ePrint Archive, Report 2009/510, 2009. (ASIC)
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Liang Lu, Maire O'Neill, Earl E. Swartzlander, "ASIC Evaluation of ECHO Hash Function," IEEE International SOC Conference, 2009. (ASIC)
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Brian Baldwin, Andrew Byrne, Mark Hamilton, Neil Hanley, Robert P. McEvoy, Weibo Pan and William P. Marnane, "FPGA Implementations of SHA-3 Candidates: CubeHash, Grostl, LANE, Shabal and Spectral Hash," 2009 12th Euromicro Conference on Digital System Design / Architectures, Methods and Tools, 2009. (FPGA)
  2008
[PDF]
Z. Chen, S. Morozov, P. Schaumont, "A Hardware Interface for Hashing Algorithms", ePrint IACR Archive, 2008/529, December 2008.
   
Related Websites
 
  NIST SHA-3 Competition Official Website
  ATHENa by George Mason University, USA
  eBASH (ECRYPT Benchmarking of All Submitted Hashes)Project
  XBX: eXternal Benchmarking eXtension (for Embedded SW)
  AIST RCIS: SHA-3 Project
  SHA-3 Hardware Evaluation by ETH Zurich
  SHA-3 Harware Benchmarking by IAIK
 

SHA-3 Hardware Project by University College Cork, Ireland

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Last updated on: Feb. 5, 2012

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