Performance Evaluation of Cryptographic Hardware and Software

-- Performance Evaluation of SHA-3 Candidates in ASIC and FPGA

Xu Guo, Meeta Srivastav, Sinan Huang, Dinesh Ganta, Michael B. Henry, Leyla Nazhandali, and Patrick Schaumont

Center for Embedded Systems for Critical Applications (CESCA), ECE, Virginia Tech

Project Sponsor: National Institute of Standards and Technology (NIST)

This chip was developed as part of the NIST sponsored project, 'Environment for Fair and Comprehensive Performance Evaluation of Cryptographic Hardware and Software'. The SHA-3 ASIC is manufactured using IBM MOSIS 0.13um CMR8SF-RVT process with ARM's Artisan SAGE-X V2.0 standard-cell library. It contains all the SHA-3 five finalists, BLAKE-256, Grostl-256, JH-256, Keccak-256, Skein-256 using the latest Round 3 tweaks (updated in January 2011) and a reference SHA256. The SHA-3 ASIC is packaged with 160-pin QFP and designed to be compatible with the SASEBO-R platform.

• Technology: IBM MOSIS 0.13um CMR8SF-RVT
• Standard-Cell Library: ARM's Artisan SAGE-X V2.0
• Area: 5 sq.mm (Core: 1.656mm x 1.656mm)
• Package: 160-pin 28mm x 28mm QFP Open Cavity
• Voltage: 3.3V I/O and 1.2V Core
• Hash Modules: BLAKE-256, Grostl-256, JH-256, Keccak-256, Skein512-256, and SHA256 (reference)
• Compatible Test Platform: SASEBO-R Board

The SHA-3 ASIC Datasheet: Download

• Target Platform: SASEBO-R Board
• Testing Software: C# software driver running on a host PC
• Communication: USB port on SASEBO-R is used to communicate with the host PC
• Control FPGA: interface the SHA-3 ASIC with the USB port on board

The SHA-3 ASIC User Guide for SASEBO-R: Download

The SHA-3 ASIC Mounting Instructions: Download

Free SHA-3 sample chips are available upon request.

Please provide the following information in your application:

Name: ________________________

Point of Contact: ________________

Email: ________________________

Address: ______________________

Phone Number: _________________

Fax: _________________________

Intended use of the SHA3 chip:

_____________________________

Each application will be reviewed in collaboration with Virginia Tech's Office of Export and Secure Research Compliance. For approved applications, a material transfer agreement (MTA) will be made between Virginia Tech's Office of Sponsored Research, and the applicant. The chip will then be send through surface mail to the applicant.

All questions regarding the application should be directed to sha3vt@gmail.com