Performance Evaluation of Cryptographic Hardware and Software

-- Performance Evaluation of SHA-3 Candidates in ASIC and FPGA

Xu Guo, Meeta Srivastav, Sinan Huang, Dinesh Ganta, Michael B. Henry, Leyla Nazhandali, and Patrick Schaumont

Center for Embedded Systems for Critical Applications (CESCA), ECE, Virginia Tech

Project Sponsor: National Institute of Standards and Technology (NIST)

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NIST SHA-3 Second Round

Source Codes

Hardware macros for the comprehensive evaluation of 14 2nd round SHA-3 candidates were designed for high-throughput. BLAKE, CubeHash, ECHO, Groestl, Hamsi, Luffa, Shabal, Skein were designed by Ohta-Sakiyama Lab., University of elector comunications. SHAvite-3 was designed by Katholieke Universiteit Leuven (COSIC). The source codes can be used freely for research purposes. For the Keccak implementation, a VHDL source code from the Keccak Website was used. We have revised most of the codes to conform our defined standard hash interface and protocol.
 

14 Second Round SHA-3 Candidates and SHA-256 Reference Designs

  • SHA256
  • BLAKE
  • BMW
  • Cubehash
  • ECHO
  • Fugue
  • Groestl
  • Hamsi
  • JH
  • Keccak
  • Luffa
  • Shabal
  • Shavite
  • SIMD
  • Skein

A package of all the RTL source codes: Download

Simulation and Testvectors

For RTL simulation, you can find a package of testbench files with testvectors as below. The test vectors are generated from the original C reference codes.

A package of testbenches and testvectors: Download

FPGA Implementation
We developed a scripted flow for FPGA evaluation of all the 14 SHA-3 candidates. Need to install Xilinx ISE Webpack and ModelSim to run some of the following scripts from command line.
 
  • Xilinx XFLOW Package
    • Use XFLOW as scritped tool to automate the Xilinx FPGA synthesis and Place&Route
    • Generate required Post-Place&Route timing simulation and power analysis files
  • FPGA Post-Place&Route Simulation Files
    • Use ModelSim command line to run .do script to do Post-Place&Route timing simulation and generate .VCD files for power anlaysis
  • Xilinx XPower Commands
    • Use Xilinx XPower command line tool do the power estimation
ASIC Implementation
We developed a scripted flow for ASIC evaluation of all the 14 SHA-3 candidates. Need to install Synopsys Design Compiler and IC Compiler with necessary standard cell library files to run the following scripts.
 
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Last updated on: August 17, 2011

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